1. Field of the Invention
The present invention relates to reduction in electric power consumption of a semiconductor integrated circuit and a semiconductor integrated circuit device.
2. Description of the Related Art
Electric power consumption P to be consumed by an LSI (Large Scale Integrated Circuit), such as a microprocessor and a DSP (Digital Signal Processor), of a type which is operated in response to an input clock is expressed by the following equation: EQU P=f.multidot.C.multidot.V.sup.2
where f is the frequency of an internal clock, C is an effective capacity of the LSI and V is power-supply voltage.
Since the electric power consumption is in proportion to the frequency of the clock as can be understood from the foregoing equation, there have been LSIs of a type having a mode for interrupting the internal clock so as to reduce electric power consumption by interrupting the internal clock in a case where the operation of the LSI is not required. However, since interruption of the internal clock is interruption of the operation of the LSI, the foregoing method cannot reduce the electric power consumption of the LSI which is being operated.
Since the electric power consumption is in proportion to the square of the power-supply voltage, there have been LSIs of a type arranged to lower the level of internal power-supply voltage when the LSI is operated in order to reduce the electric power consumption.
However, if the level of the power-supply voltage is lowered, gate delay time in the LSI is elongated and, therefore, there arises a difficulty when the foregoing structure is applied to LSIs of a type which is operated at high speed.
As described above, the LSI involves elongation of the internal gate delay time when the internal power-supply voltage is lowered, thus resulting in the frequency, at which the LSI can be operated, being lowered. Thus, there arises a problem in that the level of the power-supply voltage for the LSI cannot easily be lowered to reduce electric power consumption. FIG. 12 is a so-called Shmoo Plot graph showing the relationship between the frequencies of a clock and power-supply voltages at which the LSI can be operated. The longer the cycle of the clock is, the lower the power-supply voltage, at which the LSI can be operated, becomes. The shorter the cycle of the clock is, the higher the power-supply voltage, at which the LSI can be operated, becomes.
To solve the foregoing problem, an integrated circuit device has been suggested which comprises a frequency detection circuit for detecting the frequency of the clock, a constant-voltage power-supply circuit for generating a plurality of constant voltages, and a power-source selection circuit for selecting the output from the constant-voltage power-supply circuit in accordance with an output from the frequency detection circuit (refer to Japanese Patent Application Laid-Open No. 58-171842).
Moreover, an electric circuit has been suggested (refer to Japanese Patent Application Laid-Open No. 4-112312) which comprises operating clock selection and generation means for selecting and switching frequencies of a plurality of operation clocks, a variable voltage power source and control means for controlling the level of the output voltage from the variable voltage power source in accordance with the frequency of the operation clock. An integrated circuit device has been suggested (refer to Japanese Patent Application Laid-Open No. 60-111528) which comprises a ring oscillation circuit for detecting delay time taking place in transmitting the signal and a comparison means for subjecting the oscillation cycle of the ring oscillation circuit and a reference value to a comparison to control the delay time taking place in transmitting the signal in accordance with an output from the comparison means.